------------------------------------------------------------------------------------------------------------------------ -- -- Z80命令表 -- ------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------ -- 8bit LD系 ------------------------------------------------------------ LD r,s r←s 01 r s 1 40+(r+8)+(s) LD r,n r←n 00 r 110 --- n --- 2 06+(r+8),n LD r,(HL) r←(HL) 01 r 110 1 46+(r+8) LD r,(IX+d) r←(IX+d) 11 011 101 01 r 110 --- n --- 3 DD,46+(r+8),n LD r,(IY+d) r←(IY+d) 11 111 101 01 r 110 --- n --- 3 FD,46+(r+8),n LD (HL),r (HL)←r 01 110 r 1 70+r LD (IX+d),r (IX+d)←r 11 011 101 01 110 r 3 DD,70+r LD (IY+d),r (IY+d)←r 11 111 101 01 110 r 3 FD,70+r LD (HL),n (HL)←n 00 110 110 2 36,n LD (IX+d),n (IX+d)←n 11 011 101 00 110 110 --- d --- --- n --- 4 DD.36,d,n LD (IY+d),n (IY+d)←n 11 111 101 00 110 110 --- d --- --- n --- 4 FD.36,d,n LD A,(BC) A←(BC) 00 001 010 1 0A LD A,(DE) A←(DE) 00 011 010 1 1A LD A,(mn) A←(mn) 00 111 010 --- n --- --- m --- 3 3A,n,m LD (BC),A (BC)←A 00 000 010 1 02 LD (DE),A (DE)←A 00 010 010 1 12 LD (mn),A (mn)←A 00 110 010 --- n --- --- m --- 3 32,n,m LD I,A I←A 11 101 101 01 000 111 2 ED,47 LD R,A R←A 11 101 101 01 001 111 2 ED,4F LD A,I A←I 11 101 101 01 010 111 2 ED,57 # # 0 IFF 0 - LD A,R A←R 11 101 101 01 011 111 2 ED,5F # # 0 IFF 0 - r,s Reg. 000 B 001 C 010 D 011 E 100 H 101 L 111 A ------------------------------------------------------------ -- 16bit LD系 ------------------------------------------------------------ LD rp,mn rp←mn 00 rp0 001 --- n --- --- m --- 3 01+(rp*10),n,m LD IX,mn IX←mn 11 011 101 00 100 001 --- n --- --- m --- 4 DD,21,n,m LD IY,mn IY←mn 11 111 101 00 100 001 --- n --- --- m --- 4 FD,21,n,m LD HL,(mn) H←(mn+1) 00 101 010 --- n --- --- m --- 3 2A,n,m L←(mn) LD rp,(mn) rpH←(mn+1) 11 101 101 01 rp1 011 --- n --- --- m --- 4 ED,4b+(rp*10),n,m rpL←(mn) LD IX,(mn) IXH←(mn+1) 11 011 101 00 101 010 --- n --- --- m --- 4 DD,2A,n,m IXL←(mn) LD IY,(mn) IY←(mn+1) 11 111 101 00 101 010 --- n --- --- m --- 4 FD,2A,n,m IYL←(mn) LD (mn),HL (mn+1)←H 00 100 010 --- n --- --- m --- 3 22,n,m (mn)←L LD (mn),rp (mn+1)←rpH 11 101 101 01 rp0 011 --- n --- --- m --- 4 ED,43+(rp*10),n,m (mn)←rpL LD (mn),IX (mn+1)←IXH 11 011 101 00 100 010 --- n --- --- m --- 4 DD,22,n,m (mn)←IXL LD (mn),IY (mn+1)←IYH 11 111 101 00 100 010 --- n --- --- m --- 4 FD,22,n,m (mn)←IYL LD SP,HL SP←HL 11 111 001 1 F9 LD SP,IX SP←IX 11 011 101 11 111 001 2 DD,F9 LD SP,IY SP←IY 11 111 101 11 111 001 2 FD,F9 rp Pair Reg. 00 BC 01 DE 10 HL 11 SP ------------------------------------------------------------ -- 16bit LD系(psh,pop) ------------------------------------------------------------ PUSH rq (SP-2)←rqL 11 rq0 101 1 C5+(rp*10) (SP-1)←rqH SP←SP-2 PUSH IX (SP-2)←IXL 11 101 101 11 100 101 2 DD,E5 (SP-1)←IXH SP←SP-2 PUSH IY (SP-2)←IYL 11 111 101 11 100 101 2 FD,E5 (SP-1)←IYH SP←SP-2 POP rq rqH←(SP+1) 11 rq0 001 1 C1+(rp*10) rqL←(SP) SP←SP+2 POP IX IXH←(SP+1) 11 101 101 11 101 001 2 DD,E1 IXL←(SP) SP←SP+2 POP IY IYH←(SP+1) 11 111 101 11 101 001 2 FD,E1 IYL←(SP) SP←SP+2 rq Pair Reg. 00 BC 01 DE 10 HL 11 AF ------------------------------------------------------------ -- 8bit演算系 ------------------------------------------------------------ ADD A,r A←A+r 10 000 r 1 80+r # # # V 0 # ADD A,n A←A+n 11 000 110 --- n --- 2 C6,n # # # V 0 # ADD A,(HL) A←A+(HL) 10 000 110 1 86 # # # V 0 # ADD A,(IX+d) A←A+(IX+d) 11 011 101 10 000 110 --- d --- 3 DD,86,d # # # V 0 # ADD A,(IY+d) A←A+(IY+d) 11 111 101 10 000 110 --- d --- 3 FD,86,d # # # V 0 # ADC A,s A←A+s+cf ** 001 *** ADC A,r A←A+r+cf 10 001 r 1 88+r # # # V 0 # ADC A,n A←A+n+cf 11 001 110 --- n --- 2 CE,n # # # V 0 # ADC A,(HL) A←A+(HL)+cf 10 001 110 1 8E # # # V 0 # ADC A,(IX+d) A←A+(IX+d)+cf 11 011 101 10 001 110 --- d --- 3 DD,8E,d # # # V 0 # ADC A,(IY+d) A←A+(IY+d)+cf 11 111 101 10 001 110 --- d --- 3 FD,8E,d # # # V 0 # SUB s A←A-s ** 010 *** SUB A,r A←A-r 10 010 r 1 90+r # # # V 0 # SUB A,n A←A-n 11 010 110 --- n --- 2 D6,n # # # V 0 # SUB A,(HL) A←A-(HL) 10 010 110 1 96 # # # V 0 # SUB A,(IX+d) A←A-(IX+d) 11 011 101 10 010 110 --- d --- 3 DD,96,d # # # V 0 # SUB A,(IY+d) A←A-(IY+d) 11 111 101 10 010 110 --- d --- 3 FD,96,d # # # V 0 # SBC A,s A←A-s-cf ** 011 *** SBC A,r A←A-r-cf 10 011 r 1 98+r # # # V 0 # SBC A,n A←A-n-cf 11 011 110 --- n --- 2 DE,n # # # V 0 # SBC A,(HL) A←A-(HL)-cf 10 011 110 1 9E # # # V 0 # SBC A,(IX+d) A←A-(IX+d)-cf 11 011 101 10 011 110 --- d --- 3 DD,9E,d # # # V 0 # SBC A,(IY+d) A←A-(IY+d)-cf 11 111 101 10 011 110 --- d --- 3 FD,9E,d # # # V 0 # AND s A←A and s ** 100 *** AND A,r A←A and r 10 100 r 1 A0+r # # 1 P 0 0 AND A,n A←A and n 11 100 110 --- n --- 2 E6,n # # 1 P 0 0 AND A,(HL) A←A and (HL) 10 100 110 1 A6 # # 1 P 0 0 AND A,(IX+d) A←A and (IX+d) 11 011 101 10 100 110 --- d --- 3 DD,A6,d # # 1 P 0 0 AND A,(IY+d) A←A and (IY+d) 11 111 101 10 100 110 --- d --- 3 FD,A6,d # # 1 P 0 0 XOR s A←A xor s ** 101 *** XOR A,r A←A xor r 10 101 r 1 A8+r # # 1 P 0 0 XOR A,n A←A xor n 11 101 110 --- n --- 2 EE,n # # 1 P 0 0 XOR A,(HL) A←A xor (HL) 10 101 110 1 AE # # 1 P 0 0 XOR A,(IX+d) A←A xor (IX+d) 11 011 101 10 101 110 --- d --- 3 DD,AE,d # # 1 P 0 0 XOR A,(IY+d) A←A xor (IY+d) 11 111 101 10 101 110 --- d --- 3 FD,AE,d # # 1 P 0 0 OR s A←A or s ** 110 *** OR A,r A←A or r 10 110 r 1 B0+r # # 1 P 0 0 OR A,n A←A or n 11 110 110 --- n --- 2 F6,n # # 1 P 0 0 OR A,(HL) A←A or (HL) 10 110 110 1 B6 # # 1 P 0 0 OR A,(IX+d) A←A or (IX+d) 11 011 101 10 110 110 --- d --- 3 DD,B6,d # # 1 P 0 0 OR A,(IY+d) A←A or (IY+d) 11 111 101 10 110 110 --- d --- 3 FD,B6,d # # 1 P 0 0 CP s A-s ** 111 *** CP A,r A-r 10 111 r 1 B8+r # # # V 1 # CP A,n A-n 11 111 110 --- n --- 2 FE,n # # # V 1 # CP A,(HL) A-(HL) 10 111 110 1 BE # # # V 1 # CP A,(IX+d) A-(IX+d) 11 011 101 10 111 110 --- d --- 3 DD,BE,d # # # V 1 # CP A,(IY+d) A-(IY+d) 11 111 101 10 111 110 --- d --- 3 FD,BE,d # # # V 1 # r Reg. 000 B 001 C 010 D 011 E 100 H 101 L 111 A ADD命令と同様の繰り返し s の内容 r n (HL) (IX+d) (IY+d) INC r r←r+1 00 r 100 1 04+(r*8) # # # V 0 - INC (HL) (HL)←(HL)+1 00 110 100 1 34 # # # V 0 - INC (IX+d) (IX+d)←(IX+d)+1 11 011 011 00 110 100 --- d --- 3 DD,34,d # # # V 0 - INC (IY+d) (IY+d)←(IY+d)+1 11 111 011 00 110 100 --- d --- 3 FD,34,d # # # V 0 - DEC s s←s-1 ** *** 101 DEC r r←r-1 00 r 101 1 05+(r*8) # # # V 1 - DEC (HL) (HL)←(HL)-1 00 110 101 1 35 # # # V 1 - DEC (IX+d) (IX+d)←(IX+d)-1 11 011 011 00 110 101 --- d --- 3 DD,35,d # # # V 1 - DEC (IY+d) (IY+d)←(IY+d)-1 11 111 011 00 110 101 --- d --- 3 FD,35,d # # # V 1 - INC命令と同様の繰り返し s の内容 r (HL) (IX+d) (IY+d) ------------------------------------------------------------ -- 16ビット算術演算命令 ------------------------------------------------------------ ADD HL,rp HL←HL+rp 00 rp1 001 1 09+(rx*10) - - ? - 0 # ADC HL,rp HL←HL+rp+cf 11 101 101 01 rp1 010 2 ED,4A+(rx*10) # # ? V 0 # SBC HL,rp HL←HL-rp-cf 11 101 101 01 rp0 010 2 ED,42+(rx*10) # # ? V 1 # ADD IX,rx IX←IX+rx 11 011 101 00 rx1 001 2 DD,09+(rx*10) - - ? - 0 # ADD IY,rx IY←IY+rx 11 111 101 00 rx1 001 2 FD,09+(rx*10) INC rp rp←rp+1 00 rp0 011 1 03+(rx*10) INC IX IX←IX+1 11 011 101 00 100 011 2 DD,23 INC IY IY←IY+1 11 111 101 00 100 011 2 FD,23 DEC rp rp←rp-1 00 rp1 011 1 0B+(rx*10) DEC IX IX←IX-1 11 011 101 00 101 011 2 DD,2B DEC IY IY←IY-1 11 111 101 00 101 011 2 FD,2B rp Pair Reg. 00 BC 01 DE 10 HL 11 SP rx Pair Reg. 00 BC 01 DE 10 IX 11 SP ------------------------------------------------------------ -- ジャンプ命令 ------------------------------------------------------------ JP mn PC←mn 11 000 011 --- n --- --- m --- 3 C3,n,m JP cc,mn 11 cc 010 --- n --- --- m --- 3 C2+(cc*8),n,m 条件がccならPC←mnそうでなければ何もしない cc 条件 000 NZ non zero 001 Z zero 010 NC non carry 011 C carry 100 PO parity odd 101 PE parity even 110 P sign positive 111 M sign negative JR e PC←PC+e 00 011 000 -- e-2 -- 2 18,e JR cr,e 00 1cr 000 -- e-2 -- 2 40+(cr*8),e 条件がcrならPC←PC+eそうでなければ何もしない cr 条件 00 NZ non zero 01 Z zero 10 NC non carry 11 C carry JP (HL) PC←HL 11 101 001 1 E9 JP (IX) PC←IX 11 011 101 11 101 001 2 DD,E9 JP (IY) PC←IY 11 111 101 11 101 001 2 FD,E9 DJNZ e 00 010 000 -- e-2 -- 2 10,e B←B-1 B≠0ならPC←PC+eそうでなければ何もしない ------------------------------------------------------------ -- コール命令/リターン命令 ------------------------------------------------------------ CALL mn (SP-1)←PCH (SP-2)←PCL 11 001 101 --- n --- --- m --- 3 CD,n,m SP←SP-2 PC←mn CALL cc,mn 11 cc 100 --- n --- --- m --- 3 C4+(cc*8),n,m 条件がccならCALL mnに同じそうでなければ何もしない RET PCL←(SP) PCH←(SP+1) 11 001 001 1 C9 SP←SP+2 RET cc 11 cc 000 1 C0+(cc*8) 条件がccならRETに同じそうでなければ何もしない cc 条件 000 NZ non zero 001 Z zero 010 NC non carry 011 C carry 100 PO parity odd 101 PE parity even 110 P sign positive 111 M sign negative RETI 割り込み処理からのRET 11 101 101 01 001 101 2 ED,4D RETN マスク不可割り込み処理からのRET 11 101 101 01 000 101 2 ED,45 RST p (SP-1)←PCH (SP-2)←PCL 11 t 111 　 1 C7+(T*8) SP←SP-2 PCH←0 PCL←p t = p ÷ 8 ------------------------------------------------------------ -- 入出力命令 ------------------------------------------------------------ IN A,n IN A,(n) A←(n) 11 011 011 --- n --- 2 DB,n nがAB0〜AB7 AccがAB8〜AB15 IN r,(C) r←(BC)p 11 101 101 01 r 000 2 ED,40+(r*8) # # # P 0 - INI (HL)m←(BC)p 11 101 101 10 100 010 2 ED,A2 # *1 ? ? 1 ? HL←HL+1 B←B-1 INIR INI命令をB=0まで繰り返し 11 101 101 10 110 010 2 ED,B2 0 1 ? ? 1 ? IND (HL)m←(BC)p 11 101 101 10 101 010 2 ED,AA # *1 ? ? 1 ? HL←HL-1 B←B-1 INDR IND命令をB=0まで繰り返し 11 101 101 10 111 010 2 ED,BA 0 1 ? ? 1 ? CがAB0〜AB7 BがAB8〜AB15 OUT n,A OUT (n),A (n)←A 11 010 011 --- n --- 2 D3,n nがAB0〜AB7 AccがAB8〜AB15 OUT (C),r (BC)p←r 11 101 101 01 r 001 2 ED,41+(r*8) OUTI (BC)p←(HL)m 11 101 101 10 100 011 2 ED,A3 # *1 ? ? 1 ? HL←HL+1 B←B-1 OTIR OUTI命令をB=0まで繰り返し 11 101 101 10 110 011 2 ED,B3 0 1 ? ? 1 ? OUTD (BC)p←(HL)m 11 101 101 10 101 011 2 ED,AB # *1 ? ? 1 ? HL←HL-1 B←B-1 OTDR OUTD命令をB=0まで繰り返し 11 101 101 10 111 011 2 ED,BB 0 1 ? ? 1 ? CがAB0〜AB7 BがAB8〜AB15 r Reg. 000 B 001 C 010 D 011 E 100 H 101 L 111 A (**)mはメモリアドレス、(**)pはI/Oアドレスを表わす。 *1 Bレジスタ=0なら1 ------------------------------------------------------------ -- CPU制御命令 ------------------------------------------------------------ NOP No OPeration 00 000 000 1 00 HALT CPU halted 01 110 110 1 76 NOPの無限ループ DI IFF←0 11 110 011 1 F3 EI IFF←1 11 111 011 1 FB IM 0 割り込みモード設定 11 101 101 01 000 110 2 ED,46 IMFa←0 IMFb←0 IM 1 割り込みモード設定 11 101 101 01 010 110 2 ED,56 IMFa←1 IMFb←0 IM 2 割り込みモード設定 11 101 101 01 011 110 2 ED,5E IMFa←1 IMFb←1 ------------------------------------------------------------ -- アキュムレータ操作命令 ------------------------------------------------------------ DAA パックト10進加減算の結果補正 00 100 111 1 27 # # # P - # Decimal Adjust Accumulator CPL A←not A 00 101 111 1 2F - - 1 - 1 - Aの1の補数をとる ComPLement accumulator NEG A←0-A 11 101 101 01 000 100 2 ED,44 # # # V 1 # Aの2の補数をとる NEGate accumulator CCF cf←not cf 00 111 111 1 3F - - ? - 0 # Complement Carry Flag SCF cf←1 00 110 111 1 37 - - 0 - 0 1 Set Carry Flag ------------------------------------------------------------ -- エクスチェンジ命令 ------------------------------------------------------------ EX DE,HL DE←→HL 11 101 011 1 EB EX AF,AF' AF←→AF' 00 001 000 1 08 # # # # # # 裏レジスタ EXX BC←→BC' 11 011 001 1 D9 DE←→DE' HL←→HL' EX (SP),HL H←→(SP-1) 11 100 011 1 E3 L←→(SP) EX (SP),IX IXH←→(SP-1) 11 011 101 11 100 011 2 DD,E3 IXL←→(SP) EX (SP),IY IYH←→(SP-1) 11 111 101 11 100 011 2 FD,E3 IYL←→(SP) ------------------------------------------------------------ -- ブロック転送命令/ブロックサーチ命令 ------------------------------------------------------------ LDI (DE)←(HL) 11 101 101 10 100 000 2 ED,A0 - - 0 *1 0 - HL←HL+1 DE←DE+1 BC←BC-1 LDIR LDI命令をBC=0まで繰り返し 11 101 101 10 110 000 2 ED,B0 - - 0 0 0 - LDD (DE)←(HL) 11 101 101 10 101 000 2 ED,A8 - - 0 *1 0 - HL←HL-1 DE←DE-1 BC←BC-1 LDDR LDD命令をBC=0まで繰り返し 11 101 101 10 111 000 2 ED,B8 - - 0 0 0 - CPI A-(HL) 11 101 101 10 100 001 2 ED,A1 # *2 # *1 1 - HL←HL+1 BC←BC-1 CPIR 11 101 101 10 110 001 2 ED,B1 # *2 # *1 1 - CPI命令をA=(HL)またはBC=0まで繰り返し CPD A-(HL) 11 101 101 10 101 001 2 ED,A9 # *2 # *1 1 - HL←HL-1 BC←BC-1 CPDR 11 101 101 10 111 001 2 ED,B9 # *2 # *1 1 - CPD命令をA=(HL)またはBC=0まで繰り返し *1 BCレジスタ=0なら0 *2 A=(HL)なら1 ------------------------------------------------------------ -- ビット操作命令 ------------------------------------------------------------ BIT b,r zf←not 11 001 011 01 b r 2 CB,40+(b*8)+r # # 1 # 0 - BIT b,(HL) zf←not 11 001 011 01 b 110 2 CB,46+(b*8) # # 1 # 0 - BIT b,(IX+d) zf←not 11 011 101 11 001 011 --- d --- 01 b 110 4 DD,CB,d,46+(b*8) # # 1 # 0 - BIT b,(IY+d) zf←not 11 111 101 11 001 011 --- d --- 01 b 110 4 FD,CB,d,46+(b*8) # # 1 # 0 - SET b,r rb←1 11 001 011 11 b r 2 CB,C0+(b*8)+r SET b,(HL) (HL)b←1 11 001 011 11 b 110 2 CB,C6+(b*8) SET b,(IX+d) (IX+d)b←1 11 011 101 11 001 011 --- d --- 11 b 110 4 DD,CB,d,C6+(b*8) SET b,(IY+d) (IX+d)b←1 11 111 101 11 001 011 --- d --- 11 b 110 4 FD,CB,d,C6+(b*8) r Reg 000 B 001 C 010 D 011 E 100 H 101 L 111 A 　 b Bit tested 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 ------------------------------------------------------------ -- ローテイト・シフト命令 ------------------------------------------------------------ RLCA A7 A6 A5…2 A1 A0 cf 00 000 111 1 07 - - 0 - 0 # Rotate Left Circular Accumulator RRCA A7 A6 A5…2 A1 A0 00 001 111 1 0F - - 0 - 0 # Rotate Right Circular Accumulator RLA A7 A6 A5…2 A1 A0 00 010 111 1 17 - - 0 - 0 # Rotate Left Accumulator RRA A7 A6 A5…2 A1 A0 00 011 111 1 1F - - 0 - 0 # Rotate Right Accumulator RLC r s7 s6 s5…2 s1 s0 11 001 011 00 000 r 2 CB,00+r # # 0 P 0 # RLC (HL) 11 001 011 00 000 110 2 CB,06 # # 0 P 0 # RLC (IX+d) 11 011 101 11 001 011 --- d --- 00 000 110 4 DD,CB,d,06 # # 0 P 0 # RLC (IY+d) 11 111 101 11 001 011 --- d --- 00 000 110 4 FD,CB,d,06 # # 0 P 0 # r Reg. 000 B 001 C 010 D 011 E 100 H 101 L 111 A RRC s ** 001 *** RRC r 11 001 011 00 001 r 2 CB,08+r # # 0 P 0 # RRC (HL) 11 001 011 00 001 110 2 CB,0E # # 0 P 0 # RRC (IX+d) 11 011 101 11 001 011 --- d --- 00 001 110 4 DD,CB,b,0E # # 0 P 0 # RRC (IY+d) 11 111 101 11 001 011 --- d --- 00 001 110 4 FD,CB,b,0E # # 0 P 0 # RL s ** 010 *** RL r 11 001 011 00 010 r 2 CB,10+r # # 0 P 0 # RL (HL) 11 001 011 00 010 110 2 CB,16 # # 0 P 0 # RL (IX+d) 11 011 101 11 001 011 --- d --- 00 010 110 4 DD,CB,b,16 # # 0 P 0 # RL (IY+d) 11 111 101 11 001 011 --- d --- 00 010 110 4 FD,CB,b,16 # # 0 P 0 # RR s ** 011 *** RR r 11 001 011 00 011 r 2 CB,18+r # # 0 P 0 # RR (HL) 11 001 011 00 011 110 2 CB,1E # # 0 P 0 # RR (IX+d) 11 011 101 11 001 011 --- d --- 00 011 110 4 DD,CB,b,1E # # 0 P 0 # RR (IY+d) 11 111 101 11 001 011 --- d --- 00 011 110 4 FD,CB,b,1E # # 0 P 0 # SLA s ** 100 *** SLA r 11 001 011 00 100 r 2 CB,20+r # # 0 P 0 # SLA (HL) 11 001 011 00 100 110 2 CB,26 # # 0 P 0 # SLA (IX+d) 11 011 101 11 001 011 --- d --- 00 100 110 4 DD,CB,b,26 # # 0 P 0 # SLA (IY+d) 11 111 101 11 001 011 --- d --- 00 100 110 4 FD,CB,b,26 # # 0 P 0 # SRA s ** 101 *** SRA r 11 001 011 00 101 r 2 CB,28+r # # 0 P 0 # SRA (HL) 11 001 011 00 101 110 2 CB,2E # # 0 P 0 # SRA (IX+d) 11 011 101 11 001 011 --- d --- 00 101 110 4 DD,CB,b,2E # # 0 P 0 # SRA (IY+d) 11 111 101 11 001 011 --- d --- 00 101 110 4 FD,CB,b,2E # # 0 P 0 # SRL s ** 111 *** SRL r 11 001 011 00 111 r 2 CB,38+r 0 # 0 P 0 # SRL (HL) 11 001 011 00 111 110 2 CB,3E 0 # 0 P 0 # SRL (IX+d) 11 011 101 11 001 011 --- d --- 00 111 110 4 DD,CB,b,3E 0 # 0 P 0 # SRL (IY+d) 11 111 101 11 001 011 --- d --- 00 111 110 4 FD,CB,b,3E 0 # 0 P 0 # RLC s命令と同様の繰り返し s の内容 r (HL) (IX+d) (IY+d) RRD 11 101 101 01 100 111 2 ED,67 # # 0 P 0 - RLD 11 101 101 01 101 111 2 ED,6F # # 0 P 0 - ------------------------------------------------------------------------------------------------------------------------ -- -- 未定義命令 -- ------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------ -- 8ビットロード命令 ------------------------------------------------------------ LD t,u t←u 11 011 101 01 t u 2 DD,40+(t*8)+u LD u,t u←t 11 011 101 01 u t 2 DD,40+(u*8)+t LD u,n t←n 11 011 101 00 t 110 --- n --- 3 DD,06+(t*8),n t Reg. 000 B 001 C 010 D 011 E 100 IXH 101 IXL 111 A u Reg. 100 IXH 101 IXL ------------------------------------------------------------ -- 16ビットロード命令 ------------------------------------------------------------ LD (mn),HL (mn+1)←rpH 11 101 101 01 100 011 --- n --- --- m --- 4 ED,63,n,m (mn)←rpL LD HL,(mn) rpH←(mn+1) 11 101 101 01 101 011 --- n --- --- m --- 4 ED,6B,n,m rpL←(mn) ------------------------------------------------------------ -- 8ビット算術論理演算命令 ------------------------------------------------------------ ADD A,u A←A+u 11 011 101 10 000 u 2 DD,80+u # # # V 0 # ADC A,u A←A+u+cf 11 011 101 10 001 u 2 DD,88+u # # # V 0 # SUB u A←A-u 11 011 101 10 010 u 2 DD,90+u # # # V 1 # SBC A,u A←A-u-cf 11 011 101 10 011 u 2 DD,98+u # # # V 1 # AND u A←A and u 11 011 101 10 100 u 2 DD,a0+u # # 1 P 0 0 OR u A←A or u 11 011 101 10 101 u 2 DD,a8+u # # 0 P 0 0 XOR u A←A xor u 11 011 101 10 110 u 2 DD,b0+u # # 0 P 0 0 CP u A-u 11 011 101 10 111 u 2 DD,b8+u # # # V 1 # INC u u←u+1 11 011 101 00 u 100 2 DD,04+(u*8) # # # V 0 - DEC u u←u-1 11 011 101 00 u 101 2 DD,05+(u*8) # # # V 1 - u Reg. 100 IXH 101 IXL ------------------------------------------------------------ -- ロードローテイト・ロードシフト命令 ------------------------------------------------------------ SLL r 11 001 011 00 110 r 2 CB,30+r # 0 0 P 0 # SLL (HL) 11 001 011 00 110 110 2 CB,36 # 0 0 P 0 # SLL (IX+d) 11 011 101 11 001 011 --- d --- 00 110 110 4 DD,CB,d,36 # 0 0 P 0 # LD r,RLC(IX+d) RLC (IX+d) 11 011 101 11 001 011 --- d --- 00 000 r 4 DD,CB,d,00+r # # 0 P 0 # r←(IX+d) LD r,RRC(IX+d) RRC (IX+d) 11 011 101 11 001 011 --- d --- 00 001 r 4 DD,CB,d,08+r # # 0 P 0 # r←(IX+d) LD r,RL(IX+d) RL (IX+d) 11 011 101 11 001 011 --- d --- 00 010 r 4 DD,CB,r,10+r # # 0 P 0 # r←(IX+d) LD r,RR(IX+d) RR (IX+d) 11 011 101 11 001 011 --- d --- 00 011 r 4 DD,CB,r,18+r # # 0 P 0 # r←(IX+d) LD r,SLA(IX+d) SLA (IX+d) 11 011 101 11 001 011 --- d --- 00 100 r 4 DD,CB,r,20+r # # 0 P 0 # r←(IX+d) LD r,SRA(IX+d) SRA (IX+d) 11 011 101 11 001 011 --- d --- 00 101 r 4 DD,CB,r,28+r # # 0 P 0 # r←(IX+d) LD r,SLL(IX+d) SLL (IX+d) 11 011 101 11 001 011 --- d --- 00 110 r 4 DD,CB,r,30+r # 0 0 P 0 # r←(IX+d) LD r,SRL(IX+d) SRL (IX+d) 11 011 101 11 001 011 --- d --- 00 111 r 4 DD,CB,r,38+r 0 # 0 P 0 # r←(IX+d) r Reg. 000 B 001 C 010 D 011 E 100 H 101 L 111 A ------------------------------------------------------------ -- ロードビット操作命令 ------------------------------------------------------------ BIT b,(IX+d) zf←not (IX+d)b 11 011 101 11 001 011 --- d --- 01 b *** 4 DD,CB,d,40+(b*8) # # 1 # 0 - LD r,SET b,(IX+d) (IX+d)b←1 11 011 101 11 001 011 --- d --- 11 b r 4 DD,CB,d,F0+(b*8)+r r←(IX+d) LD r,RES b,(IX+d) (IX+d)b←0 11 011 101 11 001 011 --- d --- 10 b r 4 DD,CB,d,80+(b*8)+r r←(IX+d) r Reg. 000 B 001 C 010 D 011 E 100 H 101 L 111 A b Bit tested 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 ------------------------------------------------------------ -- 入出力命令 ------------------------------------------------------------ IN (HL),(C) 11 101 101 01 110 000 2 ED,70 # # # P 0 - (BC)pポート入力値をフラグにのみ反映 OUT (C),(HL) (BC)p←0 11 101 101 01 110 001 2 ED,71 IN (HL),(C)はR800ではIN F,(C)として Z280ではTSTI (C)として定義 CがAB0〜AB7 BがAB8〜AB15